Intel LAM (Linear Address Masking) and the x86 top-byte-tag story
Intel LAM (Linear Address Masking) and the x86 top-byte-tag story
Tag
Hardware
11 notes
Scudo & friends: hardened allocators in production
Scudo & friends: hardened allocators in production
MarkUs and quarantine-style UAF prevention
MarkUs and quarantine-style UAF prevention
Intel CET Shadow Stack + IBT
Intel CET Shadow Stack + IBT
Arm PAC + BTI
Arm PAC + BTI
MTE in a Managed Runtime
MTE in a Managed Runtime
Arm MTE
Arm MTE
CHERIoT
CHERIoT
Arm Morello
Arm Morello
CHERI (Next Generation)
CHERI (Next Generation)
Hardware Capability Machines and Tagged Memory
CHERI, Morello, CHERIoT, MTE, Apple MIE, PAC/BTI, Intel CET, MarkUs, Scudo, Intel LAM.