Computer architecture
7 papers, 1967 to 2017.
- An Efficient Algorithm for Exploiting Multiple Arithmetic Units
register renaming and the common data bus, i.e. out-of-order execution
- Validity of the Single Processor Approach to Achieving Large Scale Computing Capabilities
the serial fraction bounds every speedup
- Design of Ion-Implanted MOSFET's with Very Small Physical Dimensions
shrink every dimension and the power density stays put, until it did not
- RISC I: A Reduced Instruction Set VLSI Computer
fewer instructions, executed faster, with the compiler taking the slack
- Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers
a tiny victim cache removes most conflict misses
- Two-Level Adaptive Training Branch Prediction
a history register indexing a pattern table
- In-Datacenter Performance Analysis of a Tensor Processing Unit
a systolic matrix unit, and the roofline that explains it